DS3106LN+【PDF 29/92 页】IC TIMING LINE CARD 64-LQFP

DS3106

the next data byte. If the bus master continues to demand data, the DS3106 continues to provide the data on SDO,

increment its address counter, and prefetch the following byte. After the address counter reaches 3FFFh, it rolls

over to address 0000h and continues to increment.

Early Termination of Bus Transactions. The bus master can terminate SPI bus transactions at any time by

pulling

CS high. In response to early terminations, the DS3106 resets its SPI interface logic and waits for the start

of the next transaction. If a write transaction is terminated prior to the SCLK edge that latches the LSB of a data

byte, the data byte is not written.

Design Option: Wiring SDI and SDO Together. Because communication between the bus master and the

DS3106 is half-duplex, the SDI and SDO pins can be wired together externally to reduce wire count. To support

this option, the bus master must not drive the SDI/SDO line when the DS3106 is transmitting.

AC Timing. See Table 10-9 and Figure 10-3 for AC timing specifications for the SPI interface.

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